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ltc6991 6991f typical a pplica t ion fea t ures descrip t ion timerblox: resettable, low frequency oscillator the ltc ? 6991 is a silicon oscillator with a programmable period range of 1.024ms to 9.54 hours (29.1hz to 977hz), specifically intended for long duration timing events. the ltc6991 is part of the timerblox? family of versatile silicon timing devices. a single resistor, r set , programs the ltc6991s internal master oscillator frequency. the output clock period is determined by this master oscillator and an internal frequency divider, n div , programmable to eight settings from 1 to 2 21 . t n r k ms n out div set div = = ? ? . , , , ,..., 50 1 024 18 64 2 21 ? in normal operation, the ltc6991 oscillates with a 50% duty cycle. a reset function is provided to truncate the pulse (reducing the duty cycle). the reset pin can also be used to prevent the output from oscillating. the rst and out pins can be configured for active-low or active-high operation using a polarity function. pol bit rst pin output state 0 0 oscillating 0 1 0 (reset) 1 0 1 (reset) 1 1 oscillating the ltc6991 is available in the 6-lead sot-23 (thinsot) package or a 6-lead 2mm 3mm dfn. art titles text for graphics a pplica t ions n period range: 1ms to 9.5 hours n configured with 1 to 3 resistors n <1.5% maximum frequency error n output reset function n 2.25v to 5.5v single supply operation n 55a to 80a supply current (2ms to 9.5hr clock period) n 500s start-up time n cmos output driver sources/sinks 20ma n C40c to 125c operating temperature range n available in low profile (1mm) sot-23 (thinsot?) and 2mm 3mm dfn packages n heartbeat timers n watchdog timers n intervalometers n periodic wake-up call n high vibration, high acceleration environments n portable and battery-powered equipment l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot and timerblox are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ltc6991 2.25v to 5.5v 0.1f out r1 1m r2 392k r set 715k rst gnd set out v + div c pw 470pf r pw 2.26k 6991 ta01a 60 seconds 1s pulse width t pulse r pw ? c pw 1s low frequency pulse generator clock period range over eight divider settings div pin voltage, v div (v) 0 clock period (log scale) 10sec 10min 2.5 6991 ta01b 100ms 1ms 0.625 1.25 1.875 10hr 1sec 1min 10ms 1hr
ltc6991 6991f a bsolu t e maxi m u m r a t ings supply voltage (v + ) to gnd ........................................6v maximum voltage on any pin ................ (gnd C 0.3v) v pin (v + + 0.3v) operating temperature range (note 2) l t c6991c ............................................C40c to 85c l t c6991i .............................................C40c to 85c l t c6991h .......................................... C40c to 125c (note 1) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description specified temperature range ltc6991cdcb#pbf ltc6991cdcb#trpbf ldwz 6-lead (2mm 3mm) plastic dfn 0c to 70c ltc6991idcb#pbf ltc6991idcb#trpbf ldwz 6-lead (2mm 3mm) plastic dfn C40c to 85c ltc6991hdcb#pbf ltc6991hdcb#trpbf ldwz 6-lead (2mm 3mm) plastic dfn C40c to 125c ltc6991cs6#pbf ltc6991cs6#trpbf ltdwy 6-lead plastic tsot-23 0c to 70c ltc6991is6#pbf ltc6991is6#trpbf ltdwy 6-lead plastic tsot-23 C40c to 85c ltc6991hs6#pbf ltc6991hs6#trpbf ltdwy 6-lead plastic tsot-23 C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ top view out gnd rst v + div set dcb package 6-lead (2mm s 3mm) plastic dfn 4 5 7 6 3 2 1 t jmax = 150c, ja = 64c/w, jc = 10.6c/w exposed pad (pin 7) connected to gnd, pcb connection optional rst 1 gnd 2 set 3 6 out 5 v + 4 div top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 192c/w, jc = 51c/w p in c on f igura t ion specified temperature range (note 3) ltc6991c ................................................ 0c to 70c l t c6991i .............................................C40c to 85c l t c6991h .......................................... C40c to 125c junction temperature ........................................... 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) s6 package ........................................................... 300c
ltc6991 6991f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. test conditions are v + = 2.25v to 5.5v, rst = 0v, divcode = 0 to 15 (n div = 1 to 2 21 ), r set = 50k to 800k, r load = 5k, c load = 5pf unless otherwise noted. symbol parameter conditions min typ max units t out output clock period 1.024m 34,360 seconds f out output frequency 29.1 977 hz ?f out frequency accuracy (note 4) 29.1hz f out 977hz l 0.8 1.5 2.2 % % ?f out /?t frequency drift over temperature l 0.005 %/c frequency drift over supply v + = 4.5v to 5.5v v + = 2.25v to 4.5v l l 0.23 0.06 0.55 0.16 %/v %/v period jitter (note 10) n div = 1 n div = 8 15 7 ppm rms ppm rms bw frequency modulation bandwidth 0.4 ? f out hz t s frequency change settling time (note 9) 1 cycle analog inputs v set voltage at set pin l 0.97 1.00 1.03 v ?v set /?t v set drift over temperature l 75 v/c r set frequency-setting resistor l 50 800 k v div div pin voltage l 0 v + v ?v div /?v + div pin valid code range (note 5) deviation from ideal v div /v + = (divcode + 0.5)/16 l 1.5 % div pin input current l 10 na power supply v + operating supply voltage range l 2.25 5.5 v power-on reset voltage l 1.95 v i s supply current r l = , r set = 50k v + = 5.5v v + = 2.25v l l 135 105 170 135 a a r l = , r set = 100k v + = 5.5v v + = 2.25v l l 100 80 130 105 a a r l = , r set = 800k v + = 5.5v v + = 2.25v l l 65 55 100 85 a a
ltc6991 6991f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. test conditions are v + = 2.25v to 5.5v, rst = 0v, divcode = 0 to 15 (n div = 1 to 2 21 ), r set = 50k to 800k, r load = , c load = 5pf unless otherwise noted. symbol parameter conditions min typ max units digital i/o rst pin input capacitance 2.5 pf rst pin input current rst = 0v to v + 10 na v ih high level rst pin input voltage (note 6) l 0.7 ? v + v v il low level rst pin input voltage (note 6) l 0.3 ? v + v i out(max) output output current v + = 2.7v to 5.5v 20 ma v oh high level output voltage (note 7) v + = 5.5v i out = C1ma i out = C16ma l l 5.45 4.84 5.48 5.15 v v v + = 3.3v i out = C1ma i out = C10ma l l 3.24 2.75 3.27 2.99 v v v + = 2.25v i out = C1ma i out = C8ma l l 2.17 1.58 2.21 1.88 v v v ol low level output voltage (note 7) v + = 5.5v i out = 1ma i out = 16ma l l 0.02 0.26 0.04 0.54 v v v + = 3.3v i out = 1ma i out = 10ma l l 0.03 0.22 0.05 0.46 v v v + = 2.25v i out = 1ma i out = 8ma l l 0.03 0.26 0.07 0.54 v v t rst reset propagation delay v + = 5.5v v + = 3.3v v + = 2.25v 16 24 40 ns ns ns t width minimum input pulse width v + = 3.3v 5 ns t r output rise time (note 8) v + = 5.5v v + = 3.3v v + = 2.25v 1.1 1.7 2.7 ns ns ns t f output fall time (note 8) v + = 5.5v v + = 3.3v v + = 2.25v 1.0 1.6 2.4 ns ns ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6991c is guaranteed functional over the operating temperature range of C40c to 85c. note 3: the ltc6991c is guaranteed to meet specified performance from 0c to 70c. the ltc6991c is designed, characterized and expected to meet specified performance from C40c to 85c but it is not tested or qa sampled at these temperatures. the ltc6991i is guaranteed to meet specified performance from C40c to 85c. the ltc6991h is guaranteed to meet specified performance from C40c to 125c. note 4: frequency accuracy is defined as the deviation from the f out equation, assuming r set is used to program the frequency. note 5: see operation section, table 1 and figure 2 for a full explanation of how the div pin voltage selects the value of divcode. note 6: the rst pin has hysteresis to accommodate slow rising or falling signals. the threshold voltages are proportional to v + . typical values can be estimated at any supply voltage using v rst(rising) 0.55 ? v + + 185mv and v rst(falling) 0.48 ? v + C 155mv. note 7: to conform to the logic ic standard, current out of a pin is arbitrarily given a negative value. note 8: output rise and fall times are measured between the 10% and the 90% power supply levels with 5pf output load. these specifications are based on characterization. note 9: settling time is the amount of time required for the output to settle within 1% of the final frequency after a 0.5 or 2 change in i set . note 10: jitter is the ratio of the deviation of the period to the mean of the period. this specification is based on characterization and is not 100% tested.
ltc6991 6991f typical p er f or m ance c harac t eris t ics frequency error vs r set frequency drift vs supply voltage typical v set distribution v set drift vs i set v set drift vs supply v set vs temperature frequency error vs temperature frequency error vs temperature frequency error vs temperature v + = 3.3v, r set = 200k, t a = 25c unless otherwise noted. v set (v) 0.98 0 100 50 150 200 250 0.996 1.004 1.012 1.02 0.988 6991 g06 number of units 2 lots dfn and sot-23 1274 units i set (a) 0 ?1.0 0 0.4 0.2 0.6 0.8 1.0 10 15 20 ?0.4 ?0.2 ?0.6 ?0.8 5 6992 g07 v set (mv) referenced to i set = 10a supply (v) 2 ?1.0 0 0.4 0.2 0.6 0.8 1.0 4 5 6 ?0.4 ?0.2 ?0.6 ?0.8 3 6991 g08 drift (mv) referenced to v + = 4v temperature (c) ?50 0.980 1.000 1.010 1.005 1.015 1.020 0 25 50 100 125 0.995 0.990 0.985 ?25 75 6991 g09 v set (v) 3 parts temperature (c) ?50 error (%) 1 2 3 25 75 6991 g01 0 ?1 ?25 0 50 100 125 ?2 ?3 guaranteed max over temperature guaranteed min over temperature r set = 50k 3 parts temperature (c) ?50 error (%) 1 2 3 25 75 6991 g02 0 ?1 ?25 0 50 100 125 ?2 ?3 guaranteed max over temperature guaranteed min over temperature r set = 200k 3 parts temperature (c) ?50 error (%) 1 2 3 25 75 6991 g03 0 ?1 ?25 0 50 100 125 ?2 ?3 guaranteed max over temperature guaranteed min over temperature r set = 800k 3 parts r set (k) 0 ?3 error (%) ?2 ?1 0 1 2 3 3 parts 200 400 600 800 6991 g04 guaranteed max over temperature guaranteed min over temperature supply voltage (v) 2 ?0.5 drift (%) ?0.4 ?0.2 ?0.1 0 0.5 0.2 3 4 6991 g05 ?0.3 0.3 0.4 0.1 5 6 referenced to v + = 4.5v r set = 50k r set = 200k r set = 800k
ltc6991 6991f supply current vs r set rst threshold voltage vs supply voltage typical i set current limit vs v + supply current vs supply voltage supply current vs temperature supply current vs rst pin voltage reset propagation delay (t rst ) vs supply voltage rise and fall time vs supply voltage typical p er f or m ance c harac t eris t ics v + = 3.3v, r set = 200k, t a = 25c unless otherwise noted. supply voltage (v) 2 0 power supply current (a) 25 50 75 100 125 150 3 4 5 6 6991 g10 r set = 50k r set = 100k r set = 200k r set = 800k temperature (c) ?50 power supply current (a) 100 125 150 25 75 6991 g11 75 50 ?25 0 50 100 125 25 0 5v, r set = 100k 2.5v, r set = 100k 2.5v, r set = 800k 5v, r set = 800k v rst /v + (v/v) 0 power supply current (a) 150 200 250 0.8 6991 g12 100 50 0 0.2 0.4 0.6 1.0 5v rst falling 5v rst rising 3.3v rst falling 3.3v rst rising r set = 800k r set (k) 0 0 power supply current (a) 25 50 75 100 125 150 200 400 600 800 6991 g13 v + = 5v v + = 3.3v v + = 2.5v supply voltage (v) i set (a) 6991 g15 1000 400 800 200 600 0 2 4 3 5 6 set pin shorted to gnd supply voltage (v) rst pin voltage (v) 6991 g14 3.5 1.0 2.0 3.0 0.5 1.5 2.5 0 2 4 3 5 6 positive-going negative-going supply voltage (v) 2 0 propagation delay (ns) 5 15 20 25 50 35 3 4 6991 g16 10 40 45 30 5 6 c load = 5pf supply voltage (v) rise/fall time (ns) 6991 g17 3.0 1.5 2.5 1.0 0.5 2.0 0 2 4 3 5 6 c load = 5pf t rise t fall
ltc6991 6991f output resistance vs supply current typical start-up with pol = 1 typical p er f or m ance c harac t eris t ics v + = 3.3v, r set = 200k, t a = 25c unless otherwise noted. supply voltage (v) output resistance () 6991 g22 50 25 20 35 45 5 10 15 30 40 0 2 4 3 5 6 output sourcing current output sinking current v + 1v/div out 1v/div 250s/div v + = 2.5v divcode = 15 r set = 50k 6991 g19 500s 1s (t master ) wide initial pulse p in func t ions (dcb/s6) v + (pin 1/pin 5): supply voltage (2.25v to 5.5v). this sup- ply should be kept free from noise and ripple. it should be bypassed directly to the gnd pin with a 0.1f capacitor. div (pin 2/pin 4): programmable divider and polarity input. a v + referenced a/d converter monitors the div pin voltage (v div ) to determine a 4-bit result (divcode). v div may be generated by a resistor divider between v + and gnd. use 1% resistors to ensure an accurate result. the div pin and resistors should be shielded from the out pin or any other traces that have fast edges. limit the capacitance on the div pin to less than 100pf so that v div settles quickly. the msb of divcode (pol) deter- mines the polarity of the rst and out pins. if pol = 0, rst is active-high, and forces out low. if pol = 1, rst is active-low and forces out high. set (pin 3/pin 3): frequency-setting input. the voltage on the set pin (v set ) is regulated to 1v above gnd. the amount of current sourced from the set pin (i set ) pro- grams the master oscillator frequency. the i set current range is 1.25a to 20a. the output oscillation will stop if i set drops below approximately 500na. a resistor con- nected between set and gnd is the most accurate way to set the frequency. for best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/c or better temperature coefficient. for lower ac- curacy applications an inexpensive 1% thick film resistor may be used. limit the capacitance on the set pin to less than 10pf to minimize jitter and ensure stability. capacitance less than 100pf maintains the stability of the feedback circuit regulating the v set voltage. 6991 pf ltc6991 rst gnd set out v + div c1 0.1f r set r2 r1 v + v + rst (pin 4/pin 1): output reset. the behavior of the rst pin is dependent on the polarity bit (pol). the pol bit is configured via the divcode setting. when pol = 0, setting rst high forces out low and setting rst low allows the output to oscillate. when pol = 1, rst is active low. in that case, setting rst low forces out high and setting rst high allows the output to oscillate.
ltc6991 6991f b lock diagra m (s6 package pin numbers shown) 6991 bd programmable divider fixed divider 1024 1, 8, 64, 512 4096, 2 15 , 2 18 , 2 21 master oscillator por output polarity input polarity digital filter 4-bit a/d converter pol bit r1 r2 div v + out 5 4 1 6 halt oscillator if i set < 500na mclk t master = 1s 50k v set i set = + ? i set i set v set = 1v + ? 1v 3 22 gnd set rst r set d q r v + t out p in func t ions (dcb/s6) gnd (pin 5/pin 2): ground. tie to a low inductance ground plane for best performance. out (pin 6/pin 6): oscillator output. the out pin swings from gnd to v + with an output resistance of approximately 30. when driving an led or other low impedance load a series output resistor should be used to limit source/sink current to 20ma.
ltc6991 6991f o pera t ion the ltc6991 is built around a master oscillator with a 1mhz maximum frequency. the oscillator is controlled by the set pin current (i set ) and voltage (v set ), with a 1mhz ? 50k conversion factor that is accurate to 0.8% under typical conditions. f t mhz k i v master master set set = = 1 1 50? ? ? a feedback loop maintains v set at 1v 30mv, leaving i set as the primary means of controlling the output frequency. the simplest way to generate i set is to connect a resistor (r set ) between set and gnd, such that i set = v set /r set . the master oscillator equation reduces to: f t mhz k r master master set = = 1 1 50? ? from this equation, it is clear that v set drift will not affect the output frequency when using a single program resistor (r set ). error sources are limited to r set tolerance and the inherent frequency accuracy ?f out of the ltc6991. r set may range from 50k to 800k (equivalent to i set between 1.25a and 20a). before reaching the out pin, the oscillator frequency passes through a fixed 1024 divider. the ltc6991 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 2 15 , 2 18 or 2 21 . the divider ratio n div is set by a resistor divider attached to the div pin. f mhz k n i v or t f out div set set out out = = = 1 50 1024 1 ? ? ? , ? nn k v i ms div set set 50 1 024 ? ? ? . with r set in place of v set /i set the equation reduces to: t n r k ms out div set = ? ? . 50 1 024 ? divcode the div pin connects to an internal, v + referenced 4-bit a/d converter that determines the divcode value. divcode programs two settings on the ltc6991: 1. divcode determines the output frequency divider set- ting, n div . 2. divcode determines the polarity of the rst and out pins, via the pol bit. v div may be generated by a resistor divider between v + and gnd as shown in figure 1. figure 1. simple technique for setting divcode 6991 f01 ltc6991 v + div gnd r1 r2 2.25v to 5.5v table 1 offers recommended 1% resistor values that ac- curately produce the correct voltage division as well as the corresponding n div and pol values for the recommended resistor pairs. other values may be used as long as: 1. the v div /v + ratio is accurate to 1.5% (including resis- tor tolerances and temperature effects) 2. t he driving impedance (r1||r2) does not exceed 500k. if the voltage is generated by other means (i.e., the output of a dac) it must track the v + supply voltage. the last column in table 1 shows the ideal ratio of v div to the supply voltage, which can also be calculated as: v v divcode div + = + 0 5 16 1 5 . . % for example, if the supply is 3.3v and the desired divcode is 4, v div = 0.281 ? 3.3v = 928mv 50mv. figure 2 illustrates the information in table 1, showing that n div is symmetric around the divcode midpoint.
ltc6991 0 6991f o pera t ion table 1. divcode programming divcode pol n div recommended t out r1 (k) r2 (k) v div /v + 0 0 1 1.024ms to 16.384ms open short 0.03125 0.015 1 0 8 8.192ms to 131ms 976 102 0.09375 0.015 2 0 64 65.5ms to 1.05sec 976 182 0.15625 0.015 3 0 512 524ms to 8.39sec 1000 280 0.21875 0.015 4 0 4,096 4.19sec to 67.1sec 1000 392 0.28125 0.015 5 0 32,768 33.6sec to 537sec 1000 523 0.34375 0.015 6 0 262,144 268sec to 4,295sec 1000 681 0.40625 0.015 7 0 2,097,152 2,147sec to 34,360sec 1000 887 0.46875 0.015 8 1 2,097,152 2,147sec to 34,360sec 887 1000 0.53125 0.015 9 1 262,144 268sec to 4,295sec 681 1000 0.59375 0.015 10 1 32,768 33.6sec to 537sec 523 1000 0.65625 0.015 11 1 4,096 4.19sec to 67.1sec 392 1000 0.71875 0.015 12 1 512 524ms to 8.39sec 280 1000 0.78125 0.015 13 1 64 65.5ms to 1.05sec 182 976 0.84375 0.015 14 1 8 8.192ms to 131ms 102 976 0.90625 0.015 15 1 1 1.024ms to 16.384ms short open 0.96875 0.015 0.5? v + t out (seconds) 6991 f02 1000 10000 100 10 1 0.001 0.1 0.01 increasing v div v + 0v pol bit = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pol bit = 1 figure 2. frequency range and pol bit vs divcode
ltc6991 6991f o pera t ion rst pin and polarity (pol) bit the rst pin controls the state of the ltc6991s output as seen on the out pin. the active/inactive voltage levels depend on the pol bit setting. table 2. output states pol bit rst pin output state 0 0 oscillating 0 1 0 (reset) 1 0 1 (reset) 1 1 oscillating each period of the ltc6991s internal oscillator clocks the output state latch (see block diagram). the reset pin (rst) can reset or hold off the output latch. the active state of the reset pin is determined by the polarity function (pol). similarly, the output latch is followed by a buffer that can invert the output. the output polarity is also controlled by the pol bit. if pol = 0, the reset pin is active high and the output latch is not inverted. therefore, pulling the rst pin high will reset the output latch and force the out pin low. pulling rst low will allow the output to oscillate, with the next rising edge dependent on the internal oscillator. if pol = 1, the reset pin is active low and the output latch is inverted. therefore, pulling the rst pin low will reset the output latch and force the out pin high. pulling rst high will allow the output to oscillate, with the next falling edge dependent on the internal oscillator. note that the master oscillator frequency and phase are not affected by the rst pin; the ltc6991 continues to oscillate, internally, even when rst is active. while the reset function can block an output pulse, its exact place- ment in time can only be changed by power cycling the ltc6991. t out rst out t rst t width internal oscillator 6991 f03 t out rst out t rst internal oscillator 6991 f04 figure 3. rst timing diagram (pol = 0) figure 4. rst timing diagram (pol = 1)
ltc6991 6991f changing divcode after start-up following start-up, the a/d converter will continue monitoring v div for changes. the ltc6991 will respond to divcode changes in less than one cycle. t divcode < 500 ? t master < t out the output may have an inaccurate pulse width during the frequency transition. but the transition will be glitch-free and no high or low pulse can be shorter than the mas- ter clock period. a digital filter is used to guarantee the divcode has settled to a new value before making changes to the output. start-up time when power is first applied, the power-on reset (por) circuit will initiate the start-up time, t start . the out pin is held low during this time. the typical value for t start ranges from 0.5ms to 8ms depending on the master oscil- lator frequency (independent of n div ): t start(typ) = 500 ? t master during start-up, the div pin a/d converter must determine the correct divcode before the output is enabled. the start-up time may increase if the supply or div pin volt- ages are not stable. for this reason, it is recommended to minimize the capacitance on the div pin so it will properly track v + . less than 100pf will not affect performance. start-up behavior when first powered up, the output is held low. if the po- larity is set for non-inversion (pol = 0) and the output is enabled (rst = 0) at the end of the start-up time, out will begin oscillating. if the output is being reset (rst = 1) at the end of the start-up time, the first pulse will be skipped. subsequent pulses will also be skipped until rst = 0. in inverted operation (pol = 1), the start-up sequence is similar. however, the ltc6991 does not know the correct divcode setting when first powered up, so the output defaults low. at the end of t start , the value of divcode is recognized and out goes high (inactive) because pol = 1. if rst = 1 (inactive) then out will quickly fall after a single t master cycle. if rst = 0 at the end of the start-up time, the output is held in reset and remains high. figures 7 to 10 detail the four possible start-up sequences. div 200mv/div out 1v/div 10ms/div 6991 f05 v + = 3.3v r set = 200k v + 1v/div out 1v/div 250s/div 6991 f06 v + = 2.5v divcode = 0 r set = 50k 500s figure 5. divcode change from 1 to 0 figure 6. typical start-up o pera t ion
ltc6991 6991f t out t start output disabled for integer multiple of t out output disabled for integer multiple of t out t start t start t master rst out rst out rst out rst out 6991 f07 6991 f08 6991 f09 6991 f10 t start t out t master figure 7. start-up timing diagram (rst = 0, pol = 0) figure 8. start-up timing diagram (rst = 1, pol = 0) figure 9. start-up timing diagram (rst = 0, pol = 1) figure 10. start-up timing diagram (rst = 1, pol = 1) o pera t ion
ltc6991 6991f a pplica t ions i n f or m a t ion basic operation the simplest and most accurate method to program the ltc6991 is to use a single resistor, r set , between the set and gnd pins. the design procedure is a 3-step process. first select the pol bit setting and n div value, then calculate the value for the r set resistor. step 1: select the pol bit setting the ltc6991 can operate in normal (active-high) or inverted (active-low) modes, depending on the setting of the pol bit. the best choice depends on the the application. step 2: select the n div frequency divider value as explained earlier, the voltage on the div pin sets the divcode which determines both the pol bit and the n div value. for a given output clock period, n div should be selected to be within the following range. t ms n t ms out div out 16 384 1 024 . . (1) to minimize supply current, choose the lowest n div value (generally recommended). alternatively, use table 1 as a guide to select the best n div value for the given application. with pol already chosen, this completes the selection of divcode. use table 1 to select the proper resistor divider or v div /v + ratio to apply to the div pin. step 3: calculate and select r set the final step is to calculate the correct value for r set using the following equation. r k ms t n set out div = 50 1 024. ? (2) select the standard resistor value closest to the calculated value. example: design a 1hz oscillator with minimum power consumption and active-high reset input. step 1: select the pol bit setting for noninverted (active-high) functionality, choose pol = 0. step 2: select the n div frequency divider value choose an n div value that meets the requirements of equation (1), using t out = 1000ms: 61.04 n div 976.6 potential settings for n div include 64 and 512. n div = 64 is the best choice, as it minimizes supply current by us- ing a large r set resistor. pol = 0 and n div = 64 requires divcode = 2. using table 1, choose r1 = 976k and r2 = 182k values to program divcode = 2. step 3: select r set calculate the correct value for r set using equation (2). r k ms ms k set = = 50 1 024 1000 64 763 . ? since 763k is not available as a standard 1% resistor, substitute 768k if a C0.7% frequency shift is acceptable. otherwise, select a parallel or series pair of resistors such as 576k + 187k to attain a more precise resistance. the completed design is shown in figure 11. divcode = 2 6991 f11 ltc6991 rst gnd set rst out v + div r1 976k r2 182k r set 763k 2.25v to 5.5v figure 11. 1hz oscillator
ltc6991 6991f a pplica t ions i n f or m a t ion ltc6991 as wake-up timer the output latch reset function provided by the rst pin allows the ltc6991 to enable a larger system at regular intervals. the on-time can be controlled by the system. this allows the system to shut itself down immediately after performing its tasks, reducing power consumption. figure 12 shows an example using black boxes for a switching regulator and the system being duty-cycled. in some cases, an rc filter may be necessary at the rst ltc6991 the system can extend t on as long as needed (up to 50% of t out ) v + div set out gnd rst r filt 100k r set 665k r2 681k t on t on t on 6991 f12 r1 1m r supply 4.99k 1n4733a 5.1v 3v to 20v c filt 0.1f 0.1f t out 3570 seconds switching regulator v in v out v reg v reg done/rst ltc6991 out shdn system v + done t out t out t out figure 12. powering up a system once an hour input to filter start-up glitches from the system as it is powered on. if the ltc6991 is enabling a switching regulator that can operate on supplies greater than 5.5v, it will be necessary to limit the supply voltage provided to the ltc6991. if the ltc6991 output is not heavily loaded, and if a large r set resistor is used, the supply current will not be much larger than 100a, so a simple regulator circuit can be constructed using a zener diode.
ltc6991 6991f self-resetting circuits the rst pin has hysteresis to accommodate slow-changing input voltages. furthermore, the trip points are proportional to the supply voltage (see note 6 and the rst threshold voltage vs supply voltage curve in typical performance characteristics). this allows an rc time constant at the rst input to generate a delay that is nearly independent of the supply voltage. a simple application of this technique allows the ltc6991 output to reset itself, producing a well-controlled pulse once each cycle. figures 13a and 13b show circuits that produce approximately 1s pulses once a minute. the only difference is in the pol bit setting, which controls whether the pulse is positive or negative. voltage controlled frequency with one additional resistor, the ltc6991 output frequency can be manipulated by an external voltage. as shown in figure 14, voltage v ctrl sources/sinks a current through r vco to vary the i set current, which in turn modulates the output frequency as described in equation (3). f mhz k n r r r v v out div vco vco set ctrl s = + 1 50 1024 1 ? ? ? ? ? ? eet ? ? ? ? ? ? (3) digital frequency control the control voltage can be generated by a dac (digital- to-analog converter), resulting in a digitally-controlled frequency. many dacs allow for the use of an external reference. if such a dac is used to provide the v ctrl voltage, the v set dependency can be eliminated by buffer- ing v set and using it as the dacs reference voltage, as shown in figure 15. the dacs output voltage now tracks any v set variation and eliminates it as an error source. the set pin cannot be tied directly to the reference input of the dac because the current drawn by the dacs ref input would affect the frequency. i set extremes (master oscillator frequency extremes) when operating with i set outside of the recommended 1.25a to 20a range, the master oscillator operates outside of the 62.5khz to 1mhz range in which it is most accurate. a pplica t ions i n f or m a t ion ltc6991 2.25v to 5.5v 0.1f out r1 1m r2 392k r set 715k rst gnd set out v + div c pw 470pf r pw 2.26k 6991 f13a 60 seconds 1s pulse width v rst(rising) v + t pulse = ?r pw ? c pw ? in t pulse ?2.26k ? 470pf ? in(1 ? 0.61) t pulse 1s 1? ltc6991 2.25v to 5.5v 0.1f 6991 f13b out r1 392k r2 1m 60 seconds 0.9s pulse width v rst(falling) v + t pulse = ?r pw ? c pw ? in t pulse ?2.26k ? 470pf ? in(0.43) t pulse 0.9s r set 715k rst gnd set out v + div c pw 470pf r pw 2.26k 6991 f14 ltc6991 rst gnd set out v + div r1 c1 0.1f r2 r set r vco v ctrl v + figure 13a. self-resetting circuit (divcode = 4) figure 13b. self-resetting circuit (divcode = 11) figure 14. voltage-controlled oscillator
ltc6991 6991f the oscillator can still function with reduced accuracy for i set < 1.25a. at approximately 500na, the oscillator output will be frozen in its current state. the output could halt in a high or low state. this avoids introducing short pulses when frequency modulating a very low frequency output. at the other extreme, it is not recommended to operate the master oscillator beyond 2mhz because the accuracy of the div pin adc will suffer. frequency modulation and settling time the ltc6991 will respond to changes in i set up to a C3db bandwidth of 0.4 ? f out . following a 2 or 0.5 step change in i set , the output frequency takes less than one cycle to settle to within 1% of the final value. power supply current the power supply current varies with frequency, supply voltage and output loading. it can be estimated under any condition using the following equation. this equation a pplica t ions i n f or m a t ion ? + 6991 f15 ltc6991 rst gnd set out v + div c1 0.1f r1 r2 r set v + r vco v + 0.1f 1/2 ltc6078 ltc1659 v + v cc ref gnd v out p d in clk cs/ld 1mhz ? 50k 1024 ? n div ? r vco f out = d in = 0 to 4095 ? 1 + ? r vco r set d in 4096 0.1f figure 15. digitally-controlled oscillator ignores c load (valid for c load < 1nf) and assumes the output has 50% duty cycle. i v f pf v k v r s typ master load ( ) ? ? . ? . ? + + + + + + 7 8 420 2 1 8 ? ii a set + 50 supply bypassing and pcb layout guidelines the ltc6991 is a 2.2% accurate silicon oscillator when used in the appropriate manner. the part is simple to use and by following a few rules, the expected performance is easily achieved. adequate supply bypassing and proper pcb layout are important to ensure this. figure 18 shows example pcb layouts for both the tsot-23 and dfn packages using 0603 sized passive components. the layouts assume a two layer board with a ground plane layer beneath and around the ltc6991. these layouts are a guide and need not be followed exactly.
ltc6991 6991f 1. connect the bypass capacitor, c1, directly to the v + and gnd pins using a low inductance path. the connection from c1 to the v + pin is easily done directly on the top layer. for the dfn package, c1s connection to gnd is also simply done on the top layer. for the tsot-23, out can be routed through the c1 pads to allow a good c1 gnd connection. if the pcb design rules do not allow that, c1s gnd connection can be accomplished through multiple vias to the ground plane. multiple vias for both the gnd pin connection to the ground plane and the c1 connection to the ground plane are recommended to minimize the inductance. capacitor c1 should be a 0.1f ceramic capacitor. 2. place all passive components on the top side of the board. this minimizes trace inductance. 3. place r set as close as possible to the set pin and make a direct, short connection. the set pin is a current summing node and currents injected into this pin directly modulate the operating frequency. having a short connection minimizes the exposure to signal pickup. 4. connect r set directly to the gnd pin. using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. use a ground trace to shield the set pin. this provides another layer of protection from radiated signals. 6. place r1 and r2 close to the div pin. a direct, short connection to the div pin minimizes the external signal coupling. 6991 f18 ltc6991 rst gnd set out v + div c1 0.1f r1 r2 r set v + v + div set out gnd rst c1 r1 r2 v + r set dfn package rst gnd set out v + div r2 v + r set tsot-23 package r1 c1 figure 18. supply bypassing and pcb layout a pplica t ions i n f or m a t ion
ltc6991 6991f typical a pplica t ions 5 second on/off timed relay driver r1 1m r4 15k run reset d1 1n4148 12v no coto 1022 relay 9001-12-01 l c2 0.1f 0.1f q1 2n2219a r2 392k 6991 ta02 r3 118k 5v relay enable c 1 ltc6991 rst gnd set out v + div 1.5ms radio control servo reference pulse generator reset = open run = gnd 20ms frame rate generator 1.5ms reference pulse 5v 20ms period 5v r4 976k r7 10k c1 0.01f r5 102k r6 121k 1.5ms pulse 6991 ta03 ltc6991 rst gnd set out v + div 5v r1 1m c2 0.1f r2 280k r3 146k ltc6993-1 trig gnd set out v + div
ltc6991 0 6991f typical a pplica t ions cycling (10 seconds on/off) symmetrical power supplies r8 1m r2 1k r11 5k r3 50k r6 20k ?15v in ?15v out c1 0.1f r9 392k r1 100k m4 si4435dy m3 si9410 m1 si9410 15v in 15v out m2 si4435dy f6991 ta04 r10 237k 5v ltc6991 rst gnd set out v + div isolated ac load flasher ltc6991 gnd set r set 237k v + 0.1f 5v 5v rst 5 2 10 seconds on/off 6 6 4 2 1 4 3 1 out div r3 10k open = off gnd = on r2 392k r5 5.94k u3 nte5642 isolation barrier = 7500v hot 117v ac neutral ac r6 10k r4 215 r1 1m c2 0.022f zero crossing u2 moc3041m r7 100 40w lamp 6991 ta05
ltc6991 6991f typical a pplica t ions interval (wiper) timer ltc6991 0.1f 2s 2s 5s 5s 15s 30s 1m 2m 4m 4m off 66.5k 280k 182k 182k 18.2k 1m v + rst gnd set out v + div ltc6993-1 0.1f output 1m t interval 2 seconds to 4 minutes v + 2s trig gnd set out v + div 681k 6991 ta06 383k 2s 2s 5s 15s 30s 5v 1m 2m 4m off v + 15s 30s 1m 2m off 280k 113k 133k
ltc6991 6991f dcb package 6-lead plastic dfn (2mm 3mm) (reference ltc dwg # 05-08-1715 rev a) p ackage descrip t ion 3.00 p0.10 (2 sides) 2.00 p0.10 (2 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (tbd) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom view?exposed pad 1.65 p 0.10 (2 sides) 0.75 p0.05 r = 0.115 typ r = 0.05 typ 1.35 p0.10 (2 sides) 1 3 64 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dcb6) dfn 0405 0.25 p 0.05 0.50 bsc pin 1 notch r0.20 or 0.25 s 45o chamfer 0.25 p 0.05 1.35 p0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p0.05 (2 sides) 2.15 p0.05 0.70 p0.05 3.55 p0.05 package outline 0.50 bsc
ltc6991 6991f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
ltc6991 6991f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0910 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc1799 1mhz to 33mhz thinsot silicon oscillator wide frequency range ltc6900 1mhz to 20mhz thinsot silicon oscillator low power, wide frequency range ltc6906/ltc6907 10khz to 1mhz or 40khz thinsot silicon oscillators micropower, i supply = 35a at 400khz ltc6930 fixed frequency oscillator, 32.768khz to 8.192mhz 0.09% accuracy, 110s start-up time, 105a at 32khz ltc6990 timerblox: voltage-controlled silicon oscillator fixed-frequency or voltage-controlled operation ltc6992 timerblox: voltage-controlled pulse width modulator (pwm) simple pwm with wide frequency range ltc6993 timerblox: monostable pulse generator (one shot) resistor programmable pulse width of 1s to 34sec ltc6994 timerblox: delay block/debouncer delays rising, falling or both edges 1s to 34sec intervalometer for time-lapse photography ltc6991 1f shutter activates shutter at 8sec to 8.5min intervals r1a 332k r2 130k 6991 ta07 r s3 95.3k r s2 2m r s1 1m 8sec to 64sec rst gnd set out v + div c pw 33f r pw 100k r1b 1m ?slow range? 1.1min to 8.5 min

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